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[Communication-Mobile] DDS+PLL

Description: 基于FPGA的新的DDS+PLL时钟发生器-FPGA-based new DDS PLL clock generator
Platform: | Size: 145605 | Author: 李敏 | Hits:

[Communication] Project1-DDS

Description: 直接频率和成DDS，可以在Altera的FPGA下载实现-directly into DDS frequency and can be downloaded from Altera FPGA Implementation
Platform: | Size: 8611 | Author: lf | Hits:

[Other resource] DDS+51

Description: 本程序功能: DDS文件夹内的程序，完成直接数字频率合成功能,有正弦,三角,方波三种波形,并能扫频. 可通过键盘操作设置频率参数和选择波形种类和控制运行. 由两部分组成,\"C\"文件夹内,是用于在 51 单片机上运行的 C语言程序, \"Verilog\"文件夹内,是用Verilog语言编写的 FPGA 程序.-this program functions : DDS folder procedures, complete direct digital frequency synthesis, sine, triangle, Three square waveform, and can sweep. can be set up through the keyboard operation frequency waveform parameters and the types of choice and control operations. composed of two parts, "C" folder, for the 51 microcontroller running C Programming Language, "Verilog" folder, use the Verilog language FPGA procedures.
Platform: | Size: 1027313 | Author: 吴健 | Hits:

[Software Engineering] DDS_F_PGA

Description: DDS的FPGA实现文章 做FPGA和DDS的一参拷-DDS FPGA articles do FPGA and DDS a Senate emboss
Platform: | Size: 46090 | Author: sunny_girl | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于FPGA的DDS直接信号合成器，基于Altera CYcloneII系列-DDS direct FPGA-based signal synthesis, based on Altera CYcloneII Series
Platform: | Size: 949248 | Author: 郭强 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 关于用FPGA制作的DDS源代码。用的是verilog语言，用的是xlinx的软件-Produced with the DDS on FPGA source code. Using verilog language, using xlinx software
Platform: | Size: 5120 | Author: 张君 | Hits:

[VHDL-FPGA-Verilog] DDS-in-Verilog

Description: Verilog编写基于FPGA的DDS实现，内含源代码，希望对大家有所帮助。-DDS in Verilog FPGA-based implementation, including source code, we want to help.
Platform: | Size: 464896 | Author: haby | Hits:

[VHDL-FPGA-Verilog] DDS

Description: verilog编写，使用fpga中dds手法，可以输出任意波形的发生信号。-verilog write, use the dds fpga way, you can output an arbitrary waveform signal occurs.
Platform: | Size: 506880 | Author: 李俊 | Hits:

[Other] bishe

Description: DDS(dds)
Platform: | Size: 116736 | Author: 萨达1231 | Hits:

[VHDL-FPGA-Verilog] DDS波形发生器

Description: DDS波形生成器verilog语言书写（FPGA型号cy4以上）(DDS generate verilog)
Platform: | Size: 395264 | Author: jacktk@buaa.edu.cn | Hits:

[VHDL-FPGA-Verilog] 实验二 DDS实验

Description: FPGA 实验程序 DDS 实验程序(FPGA PROCEDURE SHANDONG UNIVERSITY)
Platform: | Size: 16808960 | Author: mengxingdeyu | Hits:

[Other] DDS

Description: 用FPGA实现的DDS，用法简单，波形稳定(DDS is implemented using FPGA)
Platform: | Size: 1977344 | Author: 刘奔 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于FPGA的DDS正弦信号设计，文件中有源代码(Design of DDS based on FPGA)
Platform: | Size: 51200 | Author: hdu | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 用verilog语言，在fpga上实现dds信号发生器，并在vga上显示出来(Verilog realizes DDS Signal Generator)
Platform: | Size: 39298048 | Author: 灵风轩允 | Hits:

[Other] DDS

Description: 描述了verilog实现的DDS信号发生器，可以经过FPGA验证，包括了代码实现以及书写。代码可以经过altera的EDA工具进行了验证，可以实现信号发生器的基本功能。希望大家珍惜，并好好学习。(Describes the Verilog implementation of the DDS signal generator, which can be verified by FPGA, including code implementation and writing. Code can be verified by the Altera EDA tool, you can achieve the basic functions of the signal generator. I hope you will cherish and study well.)
Platform: | Size: 104448 | Author: 西门电工 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 可以实现DDS 的正负线性扫频以及在线参数设置(DDS ad9914/ad9915 code)
Platform: | Size: 5120 | Author: preman | Hits:

[Other] DDS1

Description: 该文件是dds工程，用的是单片机和FPGA开发板组合实现对存储在FPGA中rom里面的波形数据的，调频率（调频范围是1-1MHz），波形在示波器上显示，单片机实现控制字的发送及控制频率，FPGA实现控制字的接收和存储波形数据,输出波形(The file is a DDS project. It is a combination of single chip microcomputer and FPGA development board to realize the amplitude modulation of the waveform data stored in the ROM in FPGA. The frequency modulation rate, the waveform shows on the oscilloscope, the MCU realizes the transmission of the control word, and the FPGA realizes the receiving and storing the waveform data of the control word.)
Platform: | Size: 1063936 | Author: Evan_Chan | Hits:

[Other] DDS

Description: DDS FPGA Verilog vhdl
Platform: | Size: 180224 | Author: 雨留兰 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 基于FPGA的DDS信号发生器，可产生频率可调的正弦波(DDS signal generator based on FPGA)
Platform: | Size: 3398656 | Author: cdy | Hits:

[VHDL-FPGA-Verilog] verilog实现dds

Description: 基于FPGA实现信号发生器的的功能，较好的参考资料。(The function of signal generator is realized based on FPGA, which is a good reference.)
Platform: | Size: 2594816 | Author: sudochang | Hits:
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